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Features
* Module Interface
- 2 full independent module capability - Common Interface Standard compliant DVB_CI (CENELEC EN-50221) NRSS-B (SCTE IS-679 Part B) DAVIC v1.2 (CA0 interface) - Memory PCMCIA compliance (R2) 8-bit data access 26-bit address Memory Card - Attribute Memory access (CIS, Tupple) - High speed capability Up to 20Mbits/s on Command Interface Up to 100Mbits/s on Transport Stream - Polling and Interrupt modes - Hot Insertion (Automatic and Reset VCC handling) - 3.3V or 5V I/O buffers * PQFP 128 package * Host microprocessor Interface - Universal Control Signal Generator (UCSG) - PC Card control signals generation - Supports PowerPC, ARM, ST20, 68xxx, TMS, LSI 64008, TC81220F, IDTR3041 host microprocessors - I2C port CIMaXTM Set-up Slot selection - Cascade mode management (up to 4 CIMaXTM) - Chip Select bank and Interrupt facilities - 3.3V or 5V I/O buffers * Digital Video Stream Interface - MPEG II Transport Stream compliant - 3.3V or 5V I/O buffer for direct interface with FEC and DEMUX ICs
Dual Common Interface Hardware ControllerCIMaxTM
T90FJR
Description
The T90FJR, also called CIMaXTM controller is the hardware extension of SCM Microsystems' second generation Common Interface integration package (CI Pack+TM). It enables CI Driver software to directly address two complete independent Common Interface modules. As such, it contributes to offer an optimized, homogeneous and complete solution for digital TV receiver manufacturer that wants quickly to implement the Common Interface. CIMaXTM includes the necessary I/Os to interface the MPEG Transport stream generated by the receiver demodulator and to daisy chain it through two modules and back it to the demultiplexer. Voltage level translators allow to avoid any additional component. CIMaXTM interfaces with major digital TV receiver microprocessors. An I2C bus is used for initialization and module selection, while a Universal Control Signal Generator (UCSG)maps CPU control bus into Command Interface control signals. To minimize pin count, host address and data buses transit through external buffers that are driven by CIMaXTM. CIMaXTM includes a memory mode that allows to use any of the two Common interface slots to read/write a 8-bit PC Card Memory card. This feature gives the receiver memory extension capability for software upgrade or better performance.
Rev. A - 7-Sep-01
1
T90FJR
In case of modules order is significant, CIMaXTM may virtually swap them (SCM' Patent Pending) after identifying which module must be in front of the transport stream. CI Pack+TM includes hardware, software and qualification tools and is suitable for Set Top box, Digital TV set or PC board.
Block Diagram
Figure 1. Block Diagram
CIMaXTM
I2C
I2C Interface
TS Module A
TS in TS out
TS interface
RST,CLK Interrupts Mngt INT
TS Module B Modules A and B Detect and Interrupt
RD,WR,CS WAIT/ACK A[25..15] UCSG Modules A and B Control Signals
Ext IT Ext CS
Buffers Control
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Pin description
Name RESET CLK SA1 SA0 SCL SDA A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 CS RD/DIR WR/STR WAIT/ACK INT EXTCS EXTINT I/O I I I I I I/O I I I I I I I I I I I I I I O O O I Type TTL TTL CMOS CMOS trig trig TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL CMOS / TS CMOS / TS CMOS / TS TTL Z Z Z Z RST CIMaXTM reset 27MHz clock input I2C address bit 2 I2C address bit 1 I2C clock I2C data Host microprocessor address bit 25 Host microprocessor address bit 24 Host microprocessor address bit 23 Host microprocessor address bit 22 Host microprocessor address bit 21 Host microprocessor address bit 20 Host microprocessor address bit 19 Host microprocessor address bit 18 Host microprocessor address bit 17 Host microprocessor address bit 16 Host microprocessor address bit 15 CIMaXTM chip select input Read strobe / transfer direction input Write strobe / transfer strobe WAIT / transfer acknowledge Interrupt output to host microprocessor External device chip select External device interrupt input Function
Name
MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3
I/O
I I I I I I I I
Type
TTL TTL TTL TTL TTL TTL TTL TTL
RST
Function
MPEG clock input from front-end MPEG packet start input MPEG valid data input MPEG data input bit 7 MPEG data input bit 6 MPEG data input bit 5 MPEG data input bit 4 MPEG data input bit 3
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Name
MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0
I/O
I I I O O O O O O O O O O O
Type
TTL TTL TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
RST
Function
MPEG data input bit 2 MPEG data input bit 1 MPEG data input bit 0
0 0 0 0 0 0 0 0 0 0 0
MPEG clock output to MPEG decoder MPEG packet start output MPEG valid data output MPEG data output bit 7 MPEG data output bit 6 MPEG data output bit 5 MPEG data output bit 4 MPEG data output bit 3 MPEG data output bit 2 MPEG data output bit 1 MPEG data output bit 0
Name
MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3
I/O
O O O O O O O O O O O I I I I I I I I
Type
CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS TTL down TTL down TTL down TTL down TTL down TTL down TTL down TTL down
RST
Z Z Z Z Z Z Z Z Z Z Z
Function
Module A MPEG clock input Module A MPEG packet start input Module A MPEG valid data input Module A MPEG data input bit 7 Module A MPEG data input bit 6 Module A MPEG data input bit 5 Module A MPEG data input bit 4 Module A MPEG data input bit 3 Module A MPEG data input bit 2 Module A MPEG data input bit 1 Module A MPEG data input bit 0 Module A MPEG clock output to MPEG decoder Module A MPEG packet start output Module A MPEG valid data output Module A MPEG data output bit 7 Module A MPEG data output bit 6 Module A MPEG data output bit 5 Module A MPEG data output bit 4 Module A MPEG data output bit 3
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Name
MDOA2 MDOA1 MDOA0 MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 MOCLKB MOSTRTB MOVALB MDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0
I/O
I I I O O O O O O O O O O O I I I I I I I I I I I
Type
TTL down TTL down TTL down CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS TTL down TTL down TTL down TTL down TTL down TTL down TTL down TTL down TTL down TTL down TTL down
RST
Function
Module A MPEG data output bit 2 Module A MPEG data output bit 1 Module A MPEG data output bit 0
Z Z Z Z Z Z Z Z Z Z Z
Module B MPEG clock input Module B MPEG packet start input Module B MPEG valid data input Module B MPEG data input bit 7 Module B MPEG data input bit 6 Module B MPEG data input bit 5 Module B MPEG data input bit 4 Module B MPEG data input bit 3 Module B MPEG data input bit 2 Module B MPEG data input bit 1 Module B MPEG data input bit 0 Module B MPEG clock output to MPEG decoder Module B MPEG packet start output Module B MPEG valid data output Module B MPEG data output bit 7 Module B MPEG data output bit 6 Module B MPEG data output bit 5 Module B MPEG data output bit 4 Module B MPEG data output bit 3 Module B MPEG data output bit 2 Module B MPEG data output bit 1 Module B MPEG data output bit 0
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T90FJR
Name
RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# RSTB CD1B# CD2B# CE1B# CE2B# RDY/IRQB# WAITB# REG# OE# WE# IORD# IOWR# VCCEN DATOE# DATDIR ADOE# ADLE
I/O
O I I O O I I O I I O O I I O O O O O O O O O O
Type
CMOS / TS CMOS trig up CMOS trig up CMOS / TS CMOS / TS TTL TTL CMOS / TS CMOS trig up CMOS trig up CMOS / TS CMOS / TS TTL TTL CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS / TS CMOS CMOS CMOS CMOS CMOS
RST
Z
Function
Module A reset Module A card detect 1 Module A card detect 2
Z Z
Module A card enable 1 Module A card enable 2 Module A Ready / IRQ signal Module A WAIT# signal
Z
Module B reset Module B card detect 1 Module B card detect 2
Z Z
Module B card enable 1 Module B card enable 2 Module B Ready / IRQ signal Module B WAIT# signal
Z Z Z Z Z Z 1 0 1 1
Modules REG# signal Modules output enable Modules write enable Modules I/O read Modules I/O write Modules VCC switch control External data buffers output enable External data buffer direction External address buffer output enable External address buffer latch enable
Name
VCC_DVB1 VCC_DVB2 VCC_CORE VCC_TSI VCC_TSO VCC_PROC GND_DVB1 GND_DVB2
I/O
Type
Power Power Power Power Power Power Power Power
Function
DVB CI modules buffers power DVB CI modules buffers power Core power MPEG input buffers power MPEG output buffers power Host microprocessor control signals buffers power DVB CI modules buffers ground DVB CI modules buffers ground
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Name
GND_CORE GND_TSI GND_TSO GND_PROC
I/O
Type
Power Power Power Power
Function
Core ground MPEG input buffers ground MPEG output buffers ground Host microprocessor control signals buffers ground
Note:
RST column indicates the output pin status after a reset issued by asserting RESET pin or RST bit in the CIMaXTM Control Register.
Notations: TTL:TTL level CMOS:CMOS level TS:Tristate trig:Schmitt Trigger up:internal pull-up down:internal pull-down
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Host microprocessor interface
Configuration interface
The CIMaXTM needs a clock source at 27MHz frequency with a duty cycle comprised between 33% and 67%. This frequency is commonly available in any digital video system. A RESET input pin (active high) is available to reset the CIMaXTM at any time when power is on (e.g. : power monitor, watchdog...). The clock must be activated before the end of the reset. The reset signal must be active during at least 16 clock cycles (600ns @ 27MHz), before CIMaXTM reset. The CIMaXTM is operational 8 cycles after reset deactivation. CIMaXTM includes an input high order address bus A[25:15] to achieve address decoding for automatic destination select or to be rerouted to the modules when using a memory PC Card with HAD=1 and TSIEN=0 and TSOEN=0, in the Module Control Register. The CIMaXTM configuration is achieved by accessing the various registers through a standard I2C interface. The I2C device address can be chosen among four values by connecting SA1 and SA0 to VCC or GND. The binary address is 1 0 0 0 0 SA1 SA0 R/W. Though, the base address can be chosen between 80h, 82h, 84h or 86h allowing the connection of up to four CIMaXTM on the same bus. Figure 2. Chronograms
SDA
tBUF tLOW tR tF tSU,STA
SCL
tHD,STA tHD,DAT tHIGH tSU,DAT tSU,STO
Parameter SCL frequency Bus free time between stop and start Hold time start condition SCL low period SCL high period Setup time before a repeated start Data hold time Data setup time Rise time for both SDA and SCL signals Fall time for both SDA and SCL signals
Symbol fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF
Min
Max 400
Unit KHz s s s s s
1.3 0.6 1.3 0.6 0.6 0 100 20 20 300 300 0.9
s ns ns ns
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Parameter Setup time before a stop condition Capacitive load for each bus line
Symbol tSU,STO Cb
Min 0.6
Max
Unit s
400
pF
Universal Control Signal Generator (UCSG)
CIMaXTM can be connected to various CPUs, each of them having a different external bus control structure with different signals and timings. To interface with a large number of different microprocessors, the host microprocessor interface includes a fully configurable UCSG block that generates the right PCMCIA control signals. At reset, the host microprocessor interface is disabled ; CS, RD/DIR and WR/STR inputs are inactive and WAIT/ACK and INT are in high impedance state. The only available access is the configuration interface (I2C) which permits to set up the CIMaXTM. Once the proper parameters have been entered in the CIMaXTM, the interface is enabled by setting the LOCK bit in the CIMaXTM Control Register (@1Fh). The access to the modules is then possible and some parameters related to the host microprocessor interface are impossible to modify. Host microprocessor input control signals are CS, RD/DIR, WR/STR and output signals are WAIT/ACK and INT. Input and output active levels can be individually set up by configuration bits. In addition, the output buffer structure is also configurable to be either open-drain (allowing wired-or) or push-pull, in the UCSG1 and UCSG2 registers. * * CS: Chip select signal indicates to the CIMaXTM that the current bus cycle is addressed to one of the modules (or external device) RD/DIR: Read strobe or direction signal. This signal function can be chosen with the RDIR bit. Read strobe indicates a valid read bus cycle or direction signal indicates the bus transfer direction when a valid bus transfer is indicated by the transfer strobe signal WR/STR: Write strobe or transfer strobe. This signal function can be adjusted with the WSTR bit. Write strobe indicates a valid write bus cycle or transfer strobe indicates a valid bus transfer in direction indicated by RD/DIR state. WAIT/ACK: Wait or Acknowledge transfer. In WAIT mode, this signal inserts wait cycles in the bus read or write operation in process. In ACK mode, this signal indicates the completion of the bus cycle. INT: Interrupt output to the host microprocessor.
*
*
*
The UCSG (universal control signals generator) inputs the RD / DIR, WR / STR and CS signals from host microprocessor, WAITA# and WAITB# from the modules and generates all the control signals to modules, host microprocessor, buffers and external device : CE1A#, CE2A#, CE1B#, CE2B#, REG#, OE#, WE#, IORD#, IOWR#, WAIT, ACK, ADLE, ADOE#, DATDIR, DATOE#. The input signals from the host microprocessor are combined, depending on the host microprocessor configuration, to form a read and write signal RD' and WR'. These signals indicate an active read or write cycle in process.
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Figure 3. Read access
t0 t1
t2
t3
t4(5) t6
t5 t8
t10 t9
RD'
WAIT(1)
ACK(1) CE(2) REG#(3) OE#(4) ADLE DATDIR DATOE# t7
Notes:
1. The WAIT/ACK output is either WAIT or ACK formatted according to the WAIT/ACK pin settings (active level, driving structure). 2. Depending on the read access type, CE can be either CE1A# or CE1B# for access to memory or IO to module A or B, CE2A# or CE2B# for access in EC (Extended Channel) mode, or even EXTCS for access to external device in regenerate mode. 3. REG# signal is not asserted during a common memory or external access. 4. OE# signal is asserted during a memory access (attribute or common). It is replaced by IORD# during an IO read cycle, an EC (Extended Channel) read cycle (using CE2A# or CE2B#) or an external access in regenerate mode. 5. t4 can be lengthened by the insertion of wait cycles. When the destination module asserts WAIT# signal, the t4 cycles counter stops until WAIT# becomes inactive anew.
Memory read timings are given for various cycle duration. In attribute memory mode, only 600ns and 300ns cycles are available. In common memory mode, 300ns doesn't exist. IO and external device in regenerate mode share the same timing specifications as they all use IORD# and IOWR# signals. Timings are given in CIMaXTM clock cycles. They are calculated to comply with PCMCIA specifications when 27MHz clock is used.
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Rev. A - 7-Sep-01
Memory read 250n s 26 ns 1.5 cycle + 26 ns (2) 3 3 14 1 1 8 1 1 7 0 26 ns 0 ns 70 ns 1.5 cycle + 26 ns 1 5 1 3 1 3 1 3 1 3 1 2 1 2 1 1 5 1 1 4 1 1 3 2 2 3 2 150 ns 100 ns IO, EC, Ext
600ns t0 max(1) t1 max t2 min t3 t4 t5 min t6 max(1) t7 min t7 max t8 max t9 t10 min
300 ns
200ns
(1) these timings are given for a load of 50 pF on WAIT/ACK pin. (1) 1.5 cycle corresponds to the start cycle detection time. t1 depends actually on the previous cycle completion which depends on t8 and t10 read timings. So t1 ranges from 3.5 to 6.5 cycles.
Note:
t0: delay between start of a read cycle and activation of WAIT t1: delay between start of a read cycle and falling edge of CE and REG# (if required for the current cycle) t2: delay between start of a read cycle and falling edge of OE# (and switching of the data buffer direction control) t3: delay between falling edge of CE and falling edge of OE# (and switching of the data buffer direction control) t4: read cycle length. This time is the necessary delay for the module to present the read data on the data output bus. After t4 delay is expired, WAIT is deasserted and ACK asserted thus enabling the processor to read the data on the bus. At the same time, ADLE is reset to latch the address presented to the module so that the data is not changed while the processor is reading. t4 can be lengthened by the module if the module requires extra wait cycles by asserting its WAIT# pin low. t5: delay to deassertion of module read signal (OE# or IORD#) after minimum delay after t4. t6: delay between end of read cycle indicated by the processor and data bus isolation (DATOE# asserted) t7: delay between data bus isolation and switching back of the data bus direction t8: delay to deassertion of module read signal (OE# or IORD#) after end of a read cycle by the processor. t9: delay between deassertion of the module read signal and deassertion of CE, REG# and ADLE (releasing the address bus) t10: delay between deassertion of the module read signal and re-enabling of the data bus (see t7 on write cycle)
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The corresponding timings are given below for a 27 MHz clock:
Memory read 250n s 26 ns 80 ns (from start cycle detection - see note in table above) 111 ns 37 ns 37 ns 37 ns 260 ns 0 ns 26 ns 0 ns 70 ns 80 ns 37 ns 37 ns 37 ns 111 ns 37 ns 37 ns 111 ns 37 ns 75 ns 37 ns 37 ns 37 ns 37 ns 150 ns 37 ns 37 ns 111 ns 75 ns 150 ns 100 ns IO, EC, Ext
600ns t0 max t1 max t2 min
300 ns
200ns
t3
111 ns
37 ns
37 ns
75 ns
t4 t5 min t6 max t7 min t7 max t8 max t9
530 ns
297 ns
185 ns
111 ns 75 ns
t10 min
185 ns
111 ns
111 ns
75 ns
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Write access
t0 t1 t2 WR' WAIT(1) ACK(1) CE(2) REG#(3) WE#(4) t7 DATOE# t3 t4(5) t5 t6
Note:
(1): The WAIT / ACK output is either WAIT or ACK formatted according to the WAIT / ACK pin settings (active level, driving structure). (2): Depending on the write access type, CE can be either CE1A# or CE1B# for access to memory or IO to module A or B, CE2A# or CE2B# for access in EC (Extended Channel) mode or even EXTCS for access to external device in regenerate mode (3): REG# signal is not asserted during a common memory or external access. (4): WE# signal is asserted during a memory access (attribute or common). It is replaced by IOWR# during an IO write cycle, an EC (Extended Channel) write cycle (using CE2A# or CE2B#) or an external access in regenerate mode. (5): t4 can be lengthened by the insertion of wait cycles. When the destination module asserts WAIT# signal, the t4 cycles counter stops until WAIT# becomes inactive anew.
Memory write is valid for both attribute and common memory access. Timings are given in CIMaXTM clock cycles. They are calculated to comply with PCMCIA specifications when 27MHz clock is used.
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Memory write 100n s IO, EC, Ext
600ns t0 max(1) t1 max t2 min t3 t4 t5 t6 max(1) t7 min 1 2 2 9 2
250ns
200ns 26 ns 1.5 cycle + 26 ns (2)
150ns
1 1 5 1
1 1 4 1 26 ns
1 1 3 1
1 1 2 1
2 2 5 1
1
1
1
1
2
Note:
1. these timings are given for a load of 50 pF on WAIT/ACK pin. 2. 1.5 cycle corresponds to the start cycle detection time. t1 depends actually on the previous cycle completion which depends on t8 and t10 read timings. So t1 ranges from 3.5 to 6.5 cycles.
Note:
t0: delay between start of a write cycle and activation of WAIT t1: delay between start of a write cycle and assertion of CE and REG# (if necessary for the current cycle) t2: delay to assertion of the write signal (WE# or IOWR#) after the start of the write cycle t3: delay to assertion of the write signal (WE# or IOWR#) after the assertion of CE t4: write cycle duration. This delay can be lengthened by the assertion of the module WAIT# pin t5: delay between deassertion of the write signal and deassertion of CE, REG# and WAIT and assertion of ACK indicating to the processor the end of its write cycle t6: delay between end of the write cycle and deassertion of ACK t7: delay between enabling of the data bus and write signal assertion. This delay is necessary when a write cycle is immediately following a read cycle (see t10 in read cycle)
The corresponding timings are given below for a 27 MHz clock:
Memory write 100n s IO, EC, Ext
600ns t0 max t1 max t2 min 75 ns
250ns
200ns 24 ns
150ns
80 ns (from start cycle detection - see note in table above) 37 ns 37 ns 37 ns 37 ns 37 ns 75 ns 37 ns 75 ns 75 ns 185 ns 37 ns
t3
75 ns
37 ns
37 ns 150 ns 37 ns 26 ns
37 ns
t4
334 ns
185 ns
111 ns
t5 t6 max
75 ns
37 ns
37 ns
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Memory write 100n s 37 ns IO, EC, Ext 75 ns
600ns t7 min 37 ns
250ns 37 ns
200ns 37 ns
150ns 37 ns
External peripheral control signals
CIMaXTM outputs a chip select EXTCS. This output is fully configurable through the Destination Select register to be open-drain or push-pull output driver and active high or low. The activation of this output can be programmed to be automatically the default selection when none of the modules is selected (bit DEF = 1 in the external access auto select mask low register) and CS input is asserted or when address match the external access auto select mask and pattern registers on the same basis as for the modules auto selection when DEF = 0. The EXTCS output can also be manually chosen to be the destination when AUTOSEL bit is 0 in the Destination Select Register and when SEL = 11. In addition, the EXTCS output can work in two ways :transmit mode or regenerate mode selected by the XCSMOD in the Destination Select Register. The EXTCS output reproduces the CS input whenever the external device selection conditions are met in the CIMaXTM, regardless of the selection mode (automatic / manual, default / pattern match). This mode permits to insert the CIMaXTM in an existing hardware architecture by replacing an existing peripheral by the CIMaXTM on the address decoder and connecting this peripheral to the CIMaXTM. The address decoding must then be set up properly on the address decoder and in the CIMaXTM to match the new hardware architecture but no extra CS is needed on the address decoder ; the CIMaXTM provides a new one in replacement of the one it needs. The following table gives the maximum propagation delay according to different conditions (70 C):
Conditions Vcc 4.5 V 4.5 V 3.0 V 3.0 V EXTCS Load 10 pF 50 pF 10 pF 50 pF CS to EXTCS maximum time 9 ns 13 ns 13 ns 16 ns
In regenerate mode, the EXTCS output acts as CEx# outputs to the modules as it is generated by the internal CIMaXTM state machine in conjunction with assertion of IORD# or IOWR#. This mode permits to access to any 8-bit peripheral accessed with a RD, a WR and a CS input such as a static RAM or an UART for example with programmable access time provided by the CIMaXTM. The CIMaXTM also provides an interrupt input. This input is rerouted to the INT output connected to the host microprocessor through the interrupt manager of the CIMaXTM. EXTINT pin is programmable to be either active-high or active-low with the EXTLVL bit in the Interrupt Config Register and is maskable with the EXTM bit in the Interrupt Mask Register. The EXTINT input status can be monitored by reading the EXT bit in the Inter-
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rupt Status Register. This feature can be used to insert the CIMaXTM in an existing environment by using an interrupt input of the host microprocessor already used by a peripheral for the CIMaXTM interrupt and connecting this peripheral's interrupt to the CIMaXTM. Using EXTCS and EXTINT enables to insert the CIMaXTM in an existing design where all the chip selects and interrupts are already affected as it virtually does not use any chip select nor interrupt.
Microprocessor
Existing connections before CIMaXTM insertion
Peripheral
CS
INT
EXTCS EXTINT
CIMaXTM
TS Daisy Chain
In the DVB Common Interface, each module has an MPEG input port constituted by MPEG clock, MPEG packet start, MPEG valid data and MPEG data bus and an MPEG output port composed of the same signals. The MPEG transport stream transits through the modules on a daisy chain basis.
Module #1
Module #2
Module #n
TS in
TS out
TS in
TS out
TS in
TS out
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Hot plug and bypass
As a module can be inserted or removed at any time, in order not to break the daisy chain, the CIMaXTM handles one MPEG transport stream bypass for each module. This bypass is enabled as long as a valid DVB CI module is not recognized to be inserted and activated in the corresponding slot or automatically as soon as the module is removed from a slot. The disabling of the bypass is controlled by the TSOEN bit in each Module Control Register. The bypass can be switched at any time, regardless of the MPEG stream synchronization.
Module #i
Control
TS in
TS out 2:1 mux
TS swap (SCM Patent Pending)
With standard conditional access modules, the order in which the transport stream passes through has no influence. However, in some particular cases, it can be useful to choose which module is first in the TS daisy chain. The TSWAP bit in the Destination Select Register when set, virtually swaps the two modules so that the MPEG stream passes first in the B module and then in the A module. The MPEG input stream pins on the module are shared with the high order addresses specified by the PC Card standard. When a module is inserted, before initialization, all these pins are forced to logical 0 state. If a memory module is recognized, the high order addresses A[25..15] can be applied to the module by setting the HAD bit in the Module Control Register. If a DVB module is recognized, the MPEG stream is applied to the module by setting the TSIEN bit in the Module Control Register. Those two bits cannot be set at the same time and are reset when the module is extracted When HAD is set, the maximum propagation delay between A[25..15] inputs and TS outputs to the modules is 25 ns with a load of 50 pF on the outputs. The TSOEN bit (TS bypass control bit) can only be set when TSIEN has previously been set. Resetting TSIEN also resets TSOEN.
TS / Addresses input signals
Invert mask
Some modules can output an MPEG stream with inverted bits in the MPEG data bus. The CIMaXTM is able to re-invert those bits to restore the correct data on the bus. This is achieved by setting the appropriate bits in the Invert Mask Register. The CIMaXTM ensures that the MPEG stream output signals applied to the modules and to the MPEG decoder (or chained CIMaXTM) meets the AC and DC electrical characteristics defined in the PC Card standard [1], the DVB CI standard [2] and Guidelines for implementation [3]. Moreover, the CIMaXTM MPEG inputs from MPEG source (e.g. front-end receiver) and from the modules comply with the same requirements. In order to fulfil the timing requirements, the MPEG stream is re-synchronized at each step
IO characteristics
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in the daisy chain, thus introducing a few MPEG clock cycles delay (1 to 3) on the data stream between the input and output depending on the number of active modules. TS signals chronograms
tclkip tclkih tclkil
MICLK
MDI, MISTRT, MIVAL
tsu
th
tclkop tclkoh tclkol
MOCLK
MDO, MOSTRT, MOVAL tckd tckd
Note:
According to Errata in EN 50221 and the Cenelec report Guidelines for implementation and use of the common interface for DVB decoder applications- CIT057 - rev6., delays for MICLK, MDI, MIVAL, MISTRT are also applicable to MOCLKA, MOCLKB, MDOA, MDOB, MOVALA, MOVALB, MOSTRTA, MOSTRB except for clock high and low times. Delays for MOCLK, MDO, MOSTRT, MOVAL are also applicable to MICLKA, MICLKB, MDIA, MDIB, MIVALA, MIVALB, MISTRTA, MISTRTB.
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Rev. A - 7-Sep-01
AC Electrical characteristics VCC = 5V, T = 25C
Parameter tclkip tclkih MPEG input clock period MICLK input clock high time MOCLKA/B input clock high time MICLK input clock low time MOCLKA/B input clock low time MPEG output clock period output clock high time output clock low time input data setup input data hold clock to data delay
Min 111 24 44 24 44 111 24 24 10 10 0
Max
Unit ns
97(1) 67 97(1) 67
ns
tclkil tclkop tclkoh tclkol tsu th tckd
ns ns
91(1) 91(1)
ns ns ns ns
15
ns
Note:
(1) for a clock period of 111 ns
19
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Rev. A - 7-Sep-01
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Command interface
The command interface is directly issued from PC Card standard [1] restricted to 8 bits access and 15 bits addressing. The command interface of a CI module is described in detail in the PC Card standard [1] and the restrictions applied to this standard for the command interface are described in the DVB CI standard [2].
Command interface signals
The 15 address bits and 8 data bits of the CI module are connected to the host microprocessor bus through buffers (type 373 and 245) which are controlled by the CIMaXTM. The CIMaXTM provides the buffers control signals: * * * * DATOE#Data Output enable (active low) ADOE# Address Output enable (active low) DATDIR Data direction according to the read/write current cycle ADLE Address Latch enable to latch the address bus until the end of the read/write cycle.
(see application note for connection of the buffers) The buffers should be powered by the same source (voltage) as the modules. The CI control signals are the same as the PC Card control signals : CE1#, CE2#, REG#, OE#, WE#, IORD#, IOWR#, RDY/IRQ#, WAIT#. The CIMaXTM generates those signals so that they fit the PC Card standard whenever the host microprocessor accesses one of the modules. The control signals activated depend on the access type chosen in the Module Control Register with ACS[1..0]. The read and write signals active level duration is configured in the memory access cycle time registers. The CIMaXTM receives RDY/IRQ# from the module and retransmits the interruption to the host microprocessor. The module can also send a WAIT# request that is also transmitted to the host microprocessor in addition to the wait states already generated due to the read and write duration.
CE1# CE2# REG# OE# WE# IORD# IOWR# RDY/IRQ# WAIT#
T90FJR CIMaXTM
Module
DATDIR DATOE # ADLE ADOE# Address bus Host microprocessor Data bus
373
245
20
Rev. A - 7-Sep-01
Registers description
CIMaXTM includes several internal registers as depicted below, and described into the following sections.
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Description Module A Control Register Module A auto select mask high Register Module A auto select mask low Register Module A auto select pattern high Register Module A auto select pattern low Register Memory access A cycle time Register Invert Input Mask A Register RFU RFU Module B Control Register Module B auto select mask high Register Module B auto select mask low Register Module B auto select pattern high Register Module B auto select pattern low Register Memory access B cycle time Register Invert Input Mask B Register RFU RFU External access auto select mask high Register External access auto select mask low Register External access auto select pattern high Register External access auto select pattern low Register RFU Destination select Register Power control Register RFU Interrupt Status Register Interrupt Mask Register Interrupt Config Register UCSG1 : Microprocessor interface config Register UCSG2 : Microprocessor wait/ack config Register CIMaXTM control Register
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Note: All registers are reset to 00h. Register bits marked X should not be set. They are read as 0. RFU = Reserved for Future Use
CIMaXTM Control Register
CIMaXTM control: (@1Fh)
This register is used to control the basic functions of CIMaXTM.
RST
X
X
X
X
X
X
LOCK
LOCK
validates and locks the chip setup 0 1 chip is not configured. Microprocessor inputs and outputs are inactive chip is configured. Configuration bits are locked and CIMaXTM IOs are active
RST
reset chip equivalent to asserting the RESET pin. CIMaXTM is reset to its initial state this bit is automatically reset; no need to write 0 in italways reads as 0 1 reset
Modules Control Registers
This register is available for each module A and B to control the initialization and access to them.
Module control : (@00h mod A, @09h mod B)
RST
TSOEN
TSIEN
HAD
ACS1
ACS0
AUTO
DET
DET
module detection read only, write has no effect 0 1 no module present module inserted
AUTO
module auto activation on detection 0 1 no auto activation procedure Interrupt is generated immediately when DET = 1 start module auto activation when DET = 1 if VCC = 1 Interrupt is generated at the end of auto activation
ACS[1:0]
module access type automatically forced to 00 when DET = 0 writing those bits is only allowed when DET = 1 00 01 10 11 access to attribute memory access to I/O space access to common memory access to Extended Channel using CE2# signal
22
Rev. A - 7-Sep-01
HAD
source selection applied to the module automatically forced to 0 when DET = 0 setting this bit is only allowed when DET = 1 and TSIEN = 0 and TSOEN = 0 0 1 apply MPEG stream apply A[25:15] for memory access
TSIEN
MPEG transport stream input control automatically forced to 0 when DET = 0 setting this bit is only allowed when DET = 1 and HAD = 0 0 1 no MPEG stream (all signals forced to 0) MPEG stream enabled
TSOEN
MPEG transport stream bypass control automatically forced to 0 when DET = 0 or TSIEN = 0 setting this bit is only allowed when DET = 1 and HAD = 0 and TSIEN = 1 0 1 bypass enabled bypass disabled (TS through module enabled)
RST
module RST pin control automatically forced to 0 when DET = 0 setting this bit is only allowed when DET = 1 The state of this bit is reproduced on the RST (A or B) pin of the module.
Invert Input Mask Register
The Invert Input Mask Register is used to complement selected bits on the incoming MPEG data stream from modules.
Invert input mask: (@06h mod A, @0Fh mod B)
INV7
INV6
INV5
INV4
INV3
INV2 INV1
INV0
INV[7:0]
Invert mask 0 1 corresponding bit is not complemented corresponding bit is complemented
23
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Destination Select Register
The Destination Select Register is used to choose which peripheral will be accessed by the microprocessor when selecting the CIMaXTM. The three available destinations are the two modules and the external device selected by the EXTCS output signal from the CIMaXTM. For each module, the access mode (memory / IO) is chosen in the Module Control Register. The destination select can be achieved either manually when AUTOSEL bit is 0 using SEL bits or automatically by configuring the select masks and patterns registers. Destination select: (@17h)
X
TSWAP
XCSDRV
XCSLVL
XCSMOD
SEL1
SEL0
AUTOSEL
AUTOSEL
automatic module selection uses high order addresses to choose module or external device (using EXTCS) 0 1 manual selection automatic selection
SEL[1:0]
module select relevant only when AUTOSEL = 0 00 01 10 11 no destination selected select module A select module B select external device using EXTCS
XCSMOD
EXTCS signal mode changing this bit is only allowed when LOCK = 0 retransmit CS signal input from processor when external device is selected or regenerate EXTCS as done for CE# signal and simultaneously generate IORD# or IOWR# 0 1 transmit mode regenerate mode
XCSLVL
EXTCS output pin active level changing this bit is only allowed when LOCK = 0 0 1 EXTCS pin is active-low EXTCS pin is active-high
XCSDRV
EXTCS output pin structure changing this bit is only allowed when LOCK = 0 0 1 EXTCS buffer is open drain EXTCS buffer is push-pull
TSWAP
TS daisy chain order swap (SCM Patent Pending)
24
Rev. A - 7-Sep-01
0 1
module A before module B module B before module A
Power Control Register
This register is used to control the power of the modules if the power switch is implemented (optional, see application note). When the VCC bit is 0, no VCC is supposed to be applied to the modules so all the outputs to the modules are in high impedance state. When VCC = 0, ADOE# and DATOE# are also high to put the address and data buffers outputs in high impedance. This implies that when no VCC switch is used, the VCC bit should anyway be set to enable the control signals to be applied to the modules.
Power control : (@18h)
VCDRV
VCLVL
X
X
X
X
X
VCC
VCC
module power supply switch control changing this bit is only allowed when LOCK = 1 0 power off 1 power on
VCLVL
module VCC output pin active level changing this bit is only allowed when LOCK = 0 0 1 VCC pin is active-low VCC pin is active-high
VCDRV
module VCC output pin structure changing this bit is only allowed when LOCK = 0 0 1 VCC buffer is open drain VCC buffer is push-pull
Module Auto Select Registers
When automatic destination selection is used, the module auto select mask indicates the high order address bits used for decoding the address windows for each module and the module auto select pattern register determines the address at which the module is addressed.
Auto select mask high : (@01h mod A, @0Ah mod B)
X
X
X
X
X
MA25
MA24
MA23
Auto select mask low : (@02h mod A, @0Bh mod B)
MA22
MA21
MA20
MA19
MA18
MA17 MA16
MA15
MA[25:15]
address mask for decoding 0 address bit doesn't care
25
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1 address bit should match programmed address bit in module auto select pattern register Auto select mask high external : (@12h)
DEF
X
X
X
X
MA25
MA24
MA23
Auto select mask low external : (@13h)
MA22
MA21
MA20
MA19
MA18
MA17
MA16
MA15
MA[25:15]
address mask for decoding relevant only when DEF = 0. Doesn't care if DEF = 1. 0 address bit doesn't care
1 address bit should match programmed address bit in module auto select pattern register DEF external device default addressing 0 EXTCS asserted when address match mask and pattern
1 EXTCS asserted when neither module A nor module B is selected while CS input active Auto select pattern high : (@03h mod A, @0Ch mod B, @14h Ext)
X
X
X
X
X
PA25
PA24
PA23
Auto select pattern low : (@04h mod A, @0Dh mod B, @15h Ext)
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA[25:15]
address pattern to match in accordance with address mask to select the corresponding module. Relevant only when DEF = 0 in external auto select mask. Doesn't care if DEF=1. When accessing a module, the CIMaXTM regenerates the module control signals and in the meantime controls the host microprocessor by inserting wait states in the microprocessor cycle or delaying the transfer acknowledge. The read or write cycle time generated by the CIMaXTM to the module can be adjusted individually for each module,
Access Time Registers
26
Rev. A - 7-Sep-01
each access type and each direction with different standard timings (refer to PC Card standard for details about timings). Memory access cycle time : (@05h mod A, @0Eh mod B)
X AM2 AM1 AM0 X CM2 CM1 CM0
AM[2:0]
attribute memory cycle time used : 000 001 010 011 100 101 to 111 100ns 150ns 200ns 250ns 600ns reserved. Do not use
This timing is valid for write access. During read access, if AM = 100, 600 ns cycles will be used, if AM = 0XX, 300ns will be used. CM[2:0] common memory cycle time used: 000 001 010 011 100 101 to 111 100ns 150ns 200ns 250ns 600ns reserved. Do not use
Interrupt Registers
The CIMaXTM handles five interrupt sources issued from modules detection, modules IRQ and external device. Each interrupt is latched in the Interrupt Status Register. Each bit in this register can generate an interrupt to the microprocessor when set and when the corresponding mask bit in the interrupt mask register is set. In addition, the interrupt output pin structure and level can be configured to match the host hardware requirements.
Interrupt status: (@1Ah) (read only)
X X X EXT IRQB IRQA DETB DETA
DETA
slot A module detection reset on read 0 no change 1 a module has been inserted or extracted in slot A
DETB
slot B module detection reset on read 0 no change
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1 a module has been inserted or extracted in slot B IRQA slot A inverted IRQ# line state 0 IRQ# on slot A is high (inactive) 1 IRQ# on slot A is low (active) IRQB slot B inverted IRQ# line state 0 IRQ# on slot B is high (inactive) 1 IRQ# on slot B is low (active) EXT EXTINT status 0 EXTINT is inactive 1 EXTINT is active
Interrupt mask register: (@1Bh)
X X X EXTM IRQBM IRQAM DETBM DETAM
DETAM
slot A module detection mask 0 1 masked unmasked : a module movement in slot A will generate an interrupt
DETBM
slot B module detection mask 0 1 masked unmasked : a module movement in slot B will generate an interrupt
IRQAM
slot A IRQ# mask 0 masked
1 unmasked : an interrupt request from module A will be transmitted to the microprocessor IRQBM slot B IRQ# mask 0 masked
1 unmasked : an interrupt request from module B will be transmitted to the microprocessor EXTM external interrupt mask 0 masked
1 unmasked : an interrupt from external source will be transmitted to the microprocessor
28
Rev. A - 7-Sep-01
Interrupt config register: (@1Ch)
X
X
X
X
X
ITDRV
ITLVL
EXTLVL
EXTLVL
EXTINT input pin active level changing this bit is only allowed when LOCK = 0 0 1 EXTINT pin is active-low EXTINT pin is active-high
ITLVL
INT output pin active level changing this bit is only allowed when LOCK = 0 0 1 INT pin is active-low INT pin is active-high
ITDRV
INT output pin structure changing this bit is only allowed when LOCK = 0 0 1 INT buffer is open drain INT buffer is push-pull
UCSG1 and UCSG2 Registers
UCSG1 Register : (@1Dh)
The UCSG1 and UCSG2 Registers generate PC Card control signals (REG#, OE#, WE#, IORD#, IOWR#, CE1/2A#, CE1/2B#) from microprocessor control signals (RD/DIR, WR/STR, WAIT/ACK, CS, A[25..15]).
X
X
X
X
CSLVL
WSTRLVL
RDIRLVL
RDIR
RDIR
RD/DIR and WR/STR inputs function changing this bit is only allowed when LOCK = 0 0 1 RD/WR mode DIR/STR mode
RDIRLVL
RD/DIR input active level (for read strobe or read direction) changing this bit is only allowed when LOCK = 0 0 1 RD is active-low or RD/DIR input is low during read transfer and high during write RD is active-high or RD/DIR input is high during read transfer and low during write
WSTRLVL
WR/STR input active level changing this bit is only allowed when LOCK = 0 0 1 WR/STR is active-low WR/STR is active-high
29
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CSLVL CS input active level changing this bit is only allowed when LOCK = 0 0 1 UCSG2 Register : (@1Eh) CS is active-low CS is active-high
X
X
X
X
X
WACK
WDRV
WLVL
WLVL
WAIT/ACK output pin active level changing this bit is only allowed when LOCK = 0 0 1 WAIT/ACK pin is active-low WAIT/ACK pin is active-high
WDRV
WAIT / ACK output pin structure changing this bit is only allowed when LOCK = 0 0 1 WAIT/ACK buffer is open drain (or open source to VCC if active high) WAIT/ACK buffer is push-pull
WACK
WAIT/ACK pin function changing this bit is only allowed when LOCK = 0 0 1 WAIT mode ACK mode
30
Rev. A - 7-Sep-01
Module Detection & Activation
Common Interface modules are hot-plugable. In order to achieve this function, the CIMaXTM automatically detects the insertion and removal of a module and acts as programmed whenever this occurs. In order to detect a module, the PC Card standard defines two reserved pins on the connector: CD1# and CD2#. They must be simultaneously asserted (grounded) to ensure a module is inserted. When a module is inserted, the CIMaXTM can automatically activate the module if programmed so when AUTO bit is asserted in the Module Control Register and VCC bit is set in the Power Control Register (modules VCC is on). The activation can also be handled manually by the host microprocessor by sequentially asserting the right bits in the Module Control Register. If both modules are inserted simultaneously, autoactivation procedure is performed sequentially on one module after the other. The module activation consists in resetting the module and waiting for RDY signal to go high with respect to the PC Card standard timings.
CD1,2#
RESET RDY/IRQ#
tbusy
th (Hi-z)
tW (RESET)
trdy
Symbol th (Hi-z) tw (RESET) tbusy (informative) trdy (informative) Reset negated to module ready Card detect to reset driven Reset pulse width Reset asserted to ready negated
Min 300 11
Max
Unit ms s
10
s
5
s
Interrupts
Interrupts are managed by CIMaXTM and one interrupt output is available for connecting CIMaXTM to the main microprocessor interrupt controller. Five interrupt sources are available : modules detection (2) modules IRQ (2) and one external device interrupt applied to the CIMaXTM by using the external interrupt input pin. Modules detection interrupts are latched inside the CIMaXTM and are acknowledged on the reading of the Interrupt Status Register. Each interrupt source can be individually masked. When masked, an incoming interrupt is visible in the Interrupt Status Register but does not generate an interrupt to the host microprocessor. The INT output to the host microprocessor can be configured to be active high or low and driven by a push-pull or an open drain.
31
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Rev. A - 7-Sep-01
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Power
The CIMaXTM has 6 power pairs (VCC - GND):
Block VCC_DVB1, Module interface VCC_DVB2, GND_DVB1, GND_DVB2 Core logic VCC_CORE, GND_CORE VCC_TSI, GND_TSI VCC_TSO, GND_TSO VCC_PROC GND_PROC
Pins
Description
Two pairs of power supplies to drive all inputs and outputs from/to the two modules
One pair for core logic
Demod interface
One pair for interfacing the TS input
Demux interface Host microprocessor interface
One pair for interfacing the TS output One pair for interfacing host microprocessor control signals
The core power pair must be connected to a 3.3V power source. The other pairs can be either connected to a 3.3V or 5V power source depending on the voltage required by the device connected to it. The DVB1 and DVB2 pairs must be connected to the same power source.
32
Rev. A - 7-Sep-01
Electrical Characteristics
Absolute Maximum Ratings
Symbol Description Storage Ambient temperature TA VDD5 VDD3 Operating Ambient temperature 5V Supply voltage Core Supply voltage I/O voltage Min Value - 50 0 -0.5 -0.5 -0.5 Max Value 150 70 5.5 3.6 VDD + 0.5 Unit C C V V V
Notice: Stresses beyond those listed values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period may affect device reliability
DC Characteristics
Specified at VDD = 5.0V (+/- 10%):
Symbol VIL VIH VOL Parameter Input low voltage Input high voltage Output low voltage IOL = 1.7 mA Output high voltage IOH = -1.7 mA Schmitt trigger positive threshold Schmitt trigger negative threshold Schmitt trigger hysteresis Input leakage current Tristate output leakage current -10 -10 0.88 0.68 10 10 0.7 x VDD 1.74 2.0 0.5 Min Type Max 0.8 Unit V V V
VOH VT+ VTVHYST IL IOZ
V V V V A A
Specified at VDD = 3.3V (+/- 10%):
Symbol VIL VIH VOL Parameter Input low voltage Input high voltage Output low voltage IOL = -2 mA Output high voltage IOH = -2 mA Schmitt trigger positive threshold Schmitt trigger negative threshold 0.88 0.7 x VDD 2.0 0.4 Min Type Max 0.8 Unit V V V
VOH
V
VT+ VT-
1.74
V
V
33
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Rev. A - 7-Sep-01
T90FJR
Symbol VHYST IL IOZ Parameter Schmitt trigger hysteresis Input leakage current Tristate output leakage current -10 -10 Min Type 0.68 10 10 Max Unit V A A
Power consumption
Some typical power consumptions are given below in the following conditions and limitations. The power consumption due to the USCG module isn't available because depending on the application. Temperature: ....................................... 25C CIMaX clock frequency: ...................... 27 MHz TS clock frequency: ............................. 2.75 MHz VCC core: ............................................ 3.3V VCC Padring: ...................................... 5V Capacitance on TS pins: ....................30 pF max Core power consumption: Icore ...................................................6.8 mA Padring power consumption: no TS activity, no module connected ...............0.0 mA TS bypassed TSin AETSout, VCC off ............... 0.67 mA TS bypassed TSin AETSout, VCC on ............... 0.75 mA TS through module A ....................................... 0.79 mA TS through modules A and B ........................... 0.83 mA
Input/Output Capacitances
The following table provides the Input and Output capacitance:
Symbol Cin Cout Cbid Description Inputs capacitance Outputs capacitance Bi-directional buffers capacitance Test condition 3.3V 3.3V 3.3V Min Type 5.4 8.6 9.6 Max Unit pF pF pF
Pull-up/pull-down
The following table provides the internal pull-up and pull-down resistor values:
Symbol up down Description pull-up resistor value pull-down resistor value Min Type 40 120 Max Unit K K
34
Rev. A - 7-Sep-01
Package
PQFP 128 pin configuration
GND_TSI MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MIVAL MISTRT MICLK VCC_TSI GND_TSO MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 MOVAL MOSTRT MOCLK VCC_TSO
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VCC_PROC GND_CORE VCC_CORE CLK RESET SA1 SA0 SCL SDA A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 CS RD/DIR WR/STR WAIT/ACK INT EXTCS EXTINT NC NC GND_PROC GND_DVB1 CD2A# CD2B# MDOA2 MDOB2 MDOA1 MDOB1 MDOA0
O
Index Mark
128 MDOB0 127 MOSTRTA 126 MOSTRTB 125 MOVALA 124 MOVALB 123 REG# 122 WAITA# 121 WAITB# 120 RSTA 119 RSTB 118 MOCLKA 117 MOCLKB 116 MDIA7 115 MDIB7 114 MDIA6 113 MDIB6 112 MDIA5 111 MDIB5 110 MICLKA 109 VCC_DVB1 108 MICLKB 107 MDIA4 106 MDIB4 105 MIVALA 104 MIVALB 103 MDIA3
35
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Rev. A - 7-Sep-01
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 MDIB3 RDY/IRQA# RDY/IRQB# MDIA2 MDIB2 WE# MDIA1 MDIB1 MDIA0 MDIB0 MISTRTA MISTRTB IOWR# IORD# OE# CE2A# GND_DVB2 CE2B# MDOA7 MDOB7 CE1A# CE1B# MDOA6 MDOB6 MDOA5 MDOB5 MDOA4 MDOB4 MDOA3 MDOB3 CD1A# CD1B# VCCEN DATOE# DATDIR ADOE# ADLE VCC_DVB2
T90FJR
Pinning
Name MDOA0 MDOB1 MDOA1 MDOB2 MDOA2 CD2B# CD2A# GND_DVB1 GND_PROC NC NC EXTINT EXTCS INT WAIT/ACK WR/STR RD/DIR CS A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 SDA SCL SA0 SA1 RESET Pin Nb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
36
Rev. A - 7-Sep-01
Name CLK VCC_CORE GND_CORE VCC_PROC GND_TSI MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MIVAL MISTRT MICLK VCC_TSI GND_TSO MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 MOVAL MOSTRT MOCLK VCC_TSO VCC_DVB2 ADLE ADOE# DATDIR DATOE#
Pin Nb 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
37
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Rev. A - 7-Sep-01
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Name VCCEN CD1B# CD1A# MDOB3 MDOA3 MDOB4 MDOA4 MDOB5 MDOA5 MDOB6 MDOA6 CE1B# CE1A# MDOB7 MDOA7 CE2B# GND_DVB2 CE2A# OE# IORD# IOWR# MISTRTB MISTRTA MDIB0 MDIA0 MDIB1 MDIA1 WE# MDIB2 MDIA2 RDY/IRQB# RDY/IRQA# MDIB3 MDIA3 MIVALB Pin Nb 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
38
Rev. A - 7-Sep-01
Name MIVALA MDIB4 MDIA4 MICLKB VCC_DVB1 MICLKA MDIB5 MDIA5 MDIB6 MDIA6 MDIB7 MDIA7 MOCLKB MOCLKA RSTB RSTA WAITB# WAITA# REG# MOVALB MOVALA MOSTRTB MOSTRTA MDOB0
Pin Nb 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
39
T90FJR
Rev. A - 7-Sep-01
T90FJR
Package outlines PQFP L 128 pin
CIMaXTM, CI PackTM and CI Pack+TM are registered trademark of SCM Microsystems. All other trademarks are the property of their respective companies.
40
Rev. A - 7-Sep-01
Atmel Wireless & Microcontrollers Sales Offices
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Web site
http://www.atmel-wm.com
(c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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